IBM39STB032xx
IBM39STB034xx
Preliminary
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
PowerPC 405B3 Host Processor Subsystem
The PowerPC 405B3 (PPC405B3) subsystem handles all system initialization and control and also provides
power and flexibility for product differentiation.
PPC405B3 Subsystem
PPC405B3 Processor
Interfaces
CPU
Interrupt Controller Interface
UIC
Clocks
Power Mgmt
Timers: PIT, FIT, 64-bit base
Multiplier/Divider
DCRs
Interrupts
JTAG (See Note)
RISC Execution Unit
Core Clocking
Thirty-two 32-bit GPRs
MMU
Data
Cache
Controls
Instruction
Cache
Controls
16KB
I-cache
8KB
D-cache
Array
Array
PLB Master
PLB Master
Note: The JTAG interface is used for development.
PowerPC 405B3 CPU
The PPC405B3 provides high performance and low power consumption. The CPU executes at sustained
speeds of greater than one cycle per instruction at 108 or 162 MHz. Interrupt latency is three cycles, the best
time for critical interrupts.
STB03_sds_041800.fm.01
April 18, 2000
Architecture and Subsystem Information
Page 5 of 55
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