IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
3.4.2 Memory Grants
Memory grants provide ingress flow control by preventing packet transmission from the attached devices
when the PowerPRS Q-64G shared memory is full. The PowerPRS Q-64G issues one memory grant for input
ports 0 to 15 and one for input ports 16 to 31. Because the packets from an attached device are routed to the
shared memory of two subswitch elements (A and B, or C and D), the PowerPRS Q-64G generates these
grants as follows:
• The PowerPRS Q-64G issues the memory grant for input ports 0 to 15 when the total packet count in the
subswitch element A shared memory and in the subswitch element B shared memory are both below the
shared memory threshold. The memory grant status is inserted into the headers of egress data, control,
service, and idle packets on ports 0 to 15.
• The PowerPRS Q-64G issues the memory grant for input ports 16 to 31 when the total packet count in
the subswitch element C shared memory and in the subswitch element D shared memory are both below
the shared memory threshold. The memory grant status is inserted into the headers of egress data, con-
trol, service, and idle packets on ports 16 to 31.
The PowerPRS Q-64G removes a memory grant when the number of packets in either subswitch element is
equal to or greater than the threshold (there is no hysteresis). When the packet count in a subswitch element
shared memory reaches the shared memory threshold, the event is reported via the corresponding shared
memory threshold exceeded bit in the Status Register (page 120). This bit generates an interrupt unless it is
masked by the corresponding bit in the Interrupt Mask Register (page 122). The programmable shared
memory threshold is accessed through the Threshold Access Register (page 114).
When programming the shared memory threshold, the number of packet store addresses reserved by the
input controllers must be subtracted from the total number of packet store addresses available in the shared
memory. (These reserved addresses store new packets during header extraction and packet retrieval.) In
the 512-Gbps configuration, 32 addresses are reserved; in the 256-Gbps configuration, 16 addresses are
reserved. Threshold programming must also consider flow control latency on the Unilinks.
To generate memory grants, the PowerPRS Q-64G continuously compares the packet count in each sub-
switch element to the shared memory threshold. However, the PowerPRS Q-64G memory grant table is
refreshed only once per packet cycle. This guarantees that all the attached devices receive the same flow
control information.
3.4.3 Multicast Grants
Multicast grants provide PowerPRS Q-64G ingress flow control by preventing multicast packets from filling
the entire shared memory. The PowerPRS Q-64G issues one multicast grant per subswitch element (A, B, C,
and D) and per priority (0 to 3). The multicast grant status for subswitch elements A and B is inserted into the
headers of egress data, control, service, and idle packets on ports 0 to 15; the multicast grant status for sub-
switch elements C and D is inserted into the headers of egress data, control, service, and idle packets on
ports 16 to 31. For each of the four subswitch elements, an internal register, MCCount, contains the differ-
ence between the total number of packet addresses in the output queues (regardless of priority or input port)
and the total number of packets stored in the shared memory.
Each priority has a multicast high threshold and a multicast low threshold that apply to all four subswitch
elements. These thresholds are accessed through the Threshold Access Register. A multicast grant for a
priority is issued when the MCCount register value falls below the multicast low threshold for that priority; a
multicast grant for a priority is removed when the MCCount register value is equal to or greater than the
Functional Description
Page 48 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
