IBM PowerPRS Q-64G
Packet Routing Switch
Preliminary
Figure 3-1. Packet Format for a 16-Gbps Port
Byte 0
H0
Byte 1
H1
Byte 2
H2/D
H2/D
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Packet 0, LU 0
Packet 1, LU 0
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Master
Unilink
H0
H1
Packet 0, LU 1
Packet 1, LU 1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Slave 1
Unilink
Packet 0, LU 7
Packet 1, LU 7
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Slave 7
Unilink
Notes:
1. Packet 0 is carried on the high channel and packet 1 is carried on the low channel.
2. There are eight logical units (LUs) per packet, and LU 0 is the master LU.
3. H0, H1, and H2 are packet header bytes; H2 exists only in the 512-Gbps configuration.
4. D is user data.
3.3 Packet Format According to Packet Type
3.3.1 General Packet Format Information
3.3.1.1 Packet Header
The master LU carries the packet header, which is comprised of the packet qualifier byte (the first byte, H0)
and either one byte (H1, in the 256-Gbps configuration) or two bytes (H1 and H2, in the 512-Gbps configura-
tion) of additional information. Depending on the packet type, the packet qualifier byte may contain informa-
tion about:
• Packet type
• Packet priority
• Header parity
• Packet color (for switchover support)
• Packet filtering information (for switchover support)
• Best-effort discard
• Extended bitmap (for packet routing)
• Flow control flywheels
The packet qualifier byte can also include reserved bits. Reserved bits pass through the device unmodified.
Unless otherwise specified, reserved bits must be set to ‘0’.
Functional Description
Page 28 of 199
prsq-64g.01.fm
December 20, 2001
IBM [ IBM ]
