IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
PLLLOCK will return to a low state if the PLL loses lock with the reference clock.
11.6 PLL Settings
The following table gives the recommended values for the IBM 28.4G Packet Routing Switch PLL settings:
Settings (PLL registers)
Reference clock
IBM 28.4G Packet Routing Switch
Switch Operating at 125 MHz Byte Clock
55 MHz
010
62.5 MHz
010
PLL RANGE A (bits [2-0])
PLL RANGE B (bits [5-3])
PLL MULT (bits [31-28])
PLL TUNE (bits [13-8])
VCO frequency
101
101
0010
0010
010011
660 MHz
010011
750 MHz
Note: If the PE PLL is used with a 55 MHz reference clock, the same settings are used except for the unused
PLL RANGE B bits.
11.6.0.1 Example of PE PLL Programming
Frequency In
50
PLL Out Frequency
100
Range
001
010
011
001
010
011
001
010
011
100
001
010
011
100
010
011
100
010
011
100
Mult
VCO
7001
600
500
7001
600
500
7701
660
550
440
7701
660
550
440
7501
625
500
7501
625
500
Tune
010011
010011
010011
010011
010010
010010
010011
010011
010011
010011
010011
010010
010010
010001
010011
010011
010011
010010
010010
010001
0010
100
55
100
110
0001
0010
110
110
0001
62.5
125
125
125
0010
0001
1. This is the recommended setting as it is the highest VCO frequency which corresponds to the minimum clock jitter
Appendix B: PLL
prssi.02.fm
March 1, 2001
Page 152 of 154
IBM [ IBM ]
