IBM3229P2035
Advance
IBM Packet Routing Switch Serial Interface Converter
11. Appendix B: PLL
11.1 PLL Configuration
During Chip POR, the PLL is held reset and stays in reset mode until a software access releases the PLL
RESET bit in the register configuration table. Before starting the PLL (by releasing the PLL RESET bit), the
PLL RANGE, PLL MULT and PLL TUNE bits must be written in the PLL register. Once the PLL is started, a
poll the PLL register for PLLLOCK bit detection. When the PLLLOCK bit is detected high, the logic clocked by
the PLL is ready to work.
11.2 PLL Reset
PLL_RESET bit [15] is provided in the register configuration table @ 90, 94, 9C. PLL RANGE [bits 5-0] and
MULT [bits 31-28] bits are provided in the register configuration table @ 90, 94, 9C. PLL TUNE bits [13-8] are
provided in the register configuration table @ 90, 94, 9C. PLLLOCK bit [14] is provided in the register config-
uration table @ 90, 94, 9C.
The RESET function puts the PLL in bypass mode so the output clock is identical to the input reference clock.
RESET should be held active (high) during power-on until all of the following condition are met: All PLL inputs
are stable and at their final values. The reference clock is stable. PLL VDDA and Vdd are at their final values.
A RESET is also required should the PLL inputs change after power-on.
11.3 PLL Range and MULT
PLL RANGE [bits 5-0] and MULT [bits 31-28] are provided in the register configuration table @ 90, 94, 9C.
Use these programmable inputs to choose the output frequency of the PLL. The logic state of these inputs
must be stable before the PLL can begin to lock.
11.4 PLL Tune
PLL TUNE bits [13-8] are provided in the register configuration table @ 90, 94, 9C. These programmable
inputs are used to optimize the PLL stability and jitter. The logic state of these inputs must be stable before
the PLL can begin to lock.
11.5 PLL LOCK
PLLLOCK bit [14] is provided in the register configuration table @ 90, 94, 9C. This signal indicates when the
feedback clock is in phase with the reference clock. While RESET is high, PLLLOCK will be low. Following
reset, PLLLOCK will stay low until lock is achieved.
The PLLLOCK signal will go high less than 300 µs after:
• The reference clock is stabilized at a constant frequency
• The RANGE and MULT inputs are at their final states
• The VDDA input is at the rail
prssi.02.fm
Appendix B: PLL
March 1, 2001
Page 151 of 154
IBM [ IBM ]
