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IBM25PPC970FX6UB186ET 参数 Datasheet PDF下载

IBM25PPC970FX6UB186ET图片预览
型号: IBM25PPC970FX6UB186ET
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 64-Bit, 1600MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576]
分类和应用: 时钟外围集成电路
文件页数/大小: 78 页 / 3525 K
品牌: IBM [ IBM ]
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Datasheet  
PowerPC 970FX RISC Microprocessor  
Table 5-1. PowerPC 970FX RISC Microprocessor Bus Configuration (Page 2 of 2)  
BUS_CFG(0:2)  
Ratio  
12:1  
Notes  
101  
110  
111  
3
1
16:1  
Not valid  
Note: BUS_CFG bits can be changed by SCOM commands during the POR sequence. See the PowerPC 970FX Power On Reset  
Application Note.  
Notes:  
1. Bus ratios of 8:1 and 16:1 are not supported for processor interface (PI) input functionality or for power tuning.  
2. Limited power-tuning frequency scaling.  
3. No power-tuning frequency scaling.  
The bus frequency multiplier ratio typically indicates the required PLL multiplier setting. Ratios based on  
multiples of 3 (3:1, 6:1, 12:1) should always use PLLMULT = ‘0’ (low) for a PLL multiplier of 12. The required  
core frequency should be divided by 12 to determine the required input SYSCLK frequency. Ratios based on  
multiples of 2 (2:1, 4:1, 8:1, 16:1) should always use PLLMULT = ‘1’ (high) to multiply SYSCLK by 8.  
Note: Using bus frequency ratios of 3:1, 6:1 or 12:1 with PLLMULT = 1 or ratios of 8:1 or 16:1 with  
PLLMULT = 0 is not recommended. Internal clock synchronization delays might reduce performance.  
After the correct BUS_CFG(0:2) and PLLMULT pin settings are determined, the required SYSCLK input  
frequency can be determined. The selected SYSCLK input frequency should be within the minimum and  
maximum frequencies specified in Table 3-8 Clock ac Timing Specifications on page 26.  
5.2.2 PLL_RANGE Configuration  
Table 5-2 shows the PLL voltage controlled oscillator (VCO) configuration for the PowerPC 970FX, using the  
pins PLL_RANGE1 and PLL_RANGE0.  
Table 5-2. PowerPC 970FX RISC Microprocessor PLL Configuration  
PLL_RANGE(1:0) Settings  
Range Name  
Low  
PLL_RANGE1  
PLL_RANGE0  
Frequency Range  
Frequency < 1.2 GHz  
1.2 GHz < Frequency < 1.8 GHz  
1.8 GHz < Frequency  
Reserved  
0
0
1
1
0
1
0
1
Medium  
High  
Reserved  
Notes:  
1. The PLL_MULT and PLL_RANGE(1:0) bits can be overwritten by JTAG commands, and the BUS_CFG bits can be changed by  
SCOM commands, during the POR sequence. See the 970FX PowerPC 970FX Power On Reset Application Note for more details.  
2. PLL frequency range settings are not an indicator of available PowerPC 970FX processor speeds.  
5.2.3 Typical PLL and SYSCLK Configurations  
Table 5-3 provides a few examples of typical system configurations.  
System Design Information  
Page 64 of 78  
Version 2.5  
March 26, 2007