Datasheet
PowerPC 970FX RISC Microprocessor
5. System Design Information
This section provides electrical and thermal design recommendations for the successful application of the
PowerPC 970FX.
5.1 External Resistors
The PowerPC 970FX contains no internal pull-up resistors for any Joint Test Action Group (JTAG), I2C, mode
select, or asynchronous inputs. System designs must include these external resistors where required. See
Table 5-6 on page 69, Table 5-7 on page 70, and Section 3.10.3 I2C and JTAG Considerations on page 43
for information about implementing external pullups and pulldowns.
5.2 Phase-Locked Loop Configuration
This section helps the user configure the phase-locked loop (PLL) and determine SYSCLK input frequency
for IBM PowerPC 970FX systems.
5.2.1 Determining PLLMULT and BUS_CFG Settings
The first step is to determine the bus frequency. This parameter is a critical component of overall system
performance. The bus should run as fast as your memory controller and bridge chip can support. When you
have determined your maximum bus frequency, select a bus multiplier ratio that will deliver the optimal
processor core frequency.
Note: The PLL_MULT and PLL_RANGE bits can be overwritten by JTAG commands, and the BUS_CFG
bits can be changed by SCOM commands, during the power-on reset (POR) sequence. See the PowerPC
970FX Power On Reset Application Note for more details.
Table 5-1 shows the available bus ratios. In most applications, this would be the highest frequency possible
for a given PowerPC 970FX part number, but other considerations (for example, available power) might take
precedence.
Table 5-1. PowerPC 970FX RISC Microprocessor Bus Configuration (Page 1 of 2)
BUS_CFG(0:2)
Ratio
2:1
Notes
000
001
010
011
100
3:1
4:1
2
2
1
6:1
8:1
Note: BUS_CFG bits can be changed by SCOM commands during the POR sequence. See the PowerPC 970FX Power On Reset
Application Note.
Notes:
1. Bus ratios of 8:1 and 16:1 are not supported for processor interface (PI) input functionality or for power tuning.
2. Limited power-tuning frequency scaling.
3. No power-tuning frequency scaling.
Version 2.5
System Design Information
Page 63 of 78
March 26, 2007
IBM [ IBM ]
