Datasheet
PowerPC 970FX RISC Microprocessor
Table 4-2. Pinout Listing for the CBGA Package (Page 4 of 5)
I/O
PI/PO
Signal Name
Pin Number
Active
Notes
5
RAMSTOP_ENABLE
RI_B
AB6
High
Low
—
Input
Input
Input
—
4
1
AA5
SPARE
AA13
W4
1, 2
7
SPARE2
—
SPARE_GND
SRESET_B
SRIN(0:1)
SRIN_B(0:1)
SROUT(0:1)
SROUT_B(0:1)
SYNC_ENABLE
SYSCLK
N1
—
—
7
AB4
Low
—
Input
—
—
—
—
—
4
L24, L21
K24, L22
L3, G1
L2, F1
AB24
R22
PI Input
PI Input
PI Output
PI Output
Input
—
—
—
High
—
Input
—
—
—
3
SYSCLK_B
TBEN
T22
—
Input
AD17
AD21
AB21
AD13
V22
High
—
Input
TCK
Input
TDI
—
Input
3
TDO
—
Output
Input
—
—
3
THERM_INT_B
TMS
Low
—
AD22
N21
Input
TRIGGERIN
TRIGGEROUT
TRST_B
High
High
Low
Input
—
—
3
N19
Output
Input
W20
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal system operation.
DD
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OV
.
DD
4. These are test signals for factory use only and must be pulled down with a 10 kΩ resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and V planes.
DD
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
Dimensions and Physical Signal Assignments
Page 58 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
