Datasheet
PowerPC 970FX RISC Microprocessor
4.3 PowerPC 970FX Microprocessor Pinout Listings
Table 4-2 provides the pinout listing for the CBGA package.
Table 4-2. Pinout Listing for the CBGA Package (Page 1 of 5)
I/O
PI/PO
Signal Name
Pin Number
Active
—
Notes
—
5
H21, J21, H22, J22, C13, A13, K22, H23, J24, G20, F23,
G21, D22, G24, G19, B15, A14, C15, D15, A16, C22,
E20, E21, B23, B24, F21, B17, B19, C14, C17, D18, B21,
D20, A22, C19, C18, A21, A23, A20, A18, A15, A17, C16,
A19
ADIN(0:43)
PI Input
N3, H2, K3, L1, M3, K4, K2, H3, H1, G4, F2, F4, E2, G3,
B8, D11, E12, A11, B10, C11, C1, C5, B2, D6, A5, A2, D2,
D8, C12, A12, B6, B4, C4, C7, A7, C8, C6, A4, A9, C9,
A10, C10, A8, A6
ADOUT(0:43)
—
PI Output
—
2
AFN
AA12
—
—
—
ANALOG_GND
ATTENTION
AVDD
R24
Analog GND
Output
AD12
High
—
—
—
1
P24
Analog V
Input
DD
AVP_RESET_B
BI_MODE_B
BUS_CFG(0:2)
BYPASS_B
W23
Low
Low
—
AC24
Input
1
AA19, AC19, AB16
Input
10
—
—
—
V24
Low
High
High
Input
C1_UND_GLOBAL
C2_UND_GLOBAL
AC16
AC15
Input
Input
Open
CHKSTOP_B
R20
Low
Drain/Bidirec-
tional
—
CKTERM_DIS
CLKIN
AA14
E24
High
—
Input
8
PI Input
—
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal system operation.
DD
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OV
.
DD
4. These are test signals for factory use only and must be pulled down with a 10 kΩ resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and V planes.
DD
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
Version 2.5
Dimensions and Physical Signal Assignments
Page 55 of 78
March 26, 2007
IBM [ IBM ]
