Datasheet
PowerPC 970FX RISC Microprocessor
Table 4-2. Pinout Listing for the CBGA Package (Page 2 of 5)
I/O
PI/PO
Signal Name
Pin Number
Active
Notes
5
CLKIN_B
CLKOUT
D24
D3
—
—
PI Input
PI Output
PI Output
Input
—
—
—
1
CLKOUT_B
DI2_B
E3
—
U24
AA1
Y1
Low
—
DIODENEG
DIODEPOS
EI_DISABLE
—
—
—
—
—
—
P20
High
Input
A3, B1, B5, B9, B12, B14, B18, B22, C3, C21, C23, D1,
D4, D10, D12, D14, D16, E5, E7, E9, E11, E13, E15, E17,
E19, E23, F6, F8, F10, F12, F14, F16, F18, F20, F22,
F24, G2, G5, G7, G9, G11, G13, G15, G17, G23, H4, H6,
H8, H10, H12, H14, H16, H18, H20, J3, J5, J7, J9, J11,
J13, J15, J17, J19, J23, K1, K6, K8, K10, K12, K14, K16,
K18, K20, L5, L7, L9, L11, L13, L15, L17, L23, M2, M4,
M6, M8, M10, M12, M14, M16, M20, M22, M24, N5, N7,
N9, N11, N13, N15, N17, N23, P4, P6, P8, P10, P12, P14,
P16, P18, P22, R3, R5, R7, R9, R11, R13, R15, R17,
R19, R21, R23, T4, T6, T8, T10, T12, T14, T16, T18, T24,
U1, U3, U5, U7, U9, U11, U13, U15, U17, U21, U23, V2,
V4, V6, V8, V10, V12, V14, V16, V18, W1, W3, W5, W7,
W9, W11, W13, W15, W17, W19, W21, Y2, Y4, Y6, Y8,
Y10, Y12, Y14, Y16, Y18, Y20, Y24, AA3, AA7, AA11,
AA15, AA17, AA21, AA23, AB2, AB8, AB10, AB14, AB18,
AB20, AB22, AC1, AC3, AC5, AC7, AC11, AC13, AC17,
AC21, AC23, AD2, AD4, AD6, AD10, AD16, AD20, AD24
GND
—
GND
—
GPULDBG
HRESET_B
AA22
V20
High
Low
Input
Input
9
—
OD
I2CCK_B
I2CDT_B
AA20
—
—
BiDi
OD
Y21
N22
—
—
—
—
BiDi
I2CGO
OD
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal system operation.
DD
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OV
.
DD
4. These are test signals for factory use only and must be pulled down with a 10 kΩ resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and V planes.
DD
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
Dimensions and Physical Signal Assignments
Page 56 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
