Datasheet
PowerPC 970FX RISC Microprocessor
Figure 3-7. Asynchronous Input Timing
2
All active
low inputs
VM
VM
3
3
1
3
2
VM
VM
All active
high inputs
Notes:
1. There is no reference to SYSCLK because these inputs are sampled using the internal processor clock.
2. Define maximum rise and fall time as < 1 ns.
3. Define minimal pulse length > 10 ns.
4. The midpoint voltage (VM) is (OV /2).
DD
5. These timings refer to the following pins: INT, MCP, QACK, HRESET ,SRESET, TBEN, THERM_INT, and TRIGGERIN.
6. The legend for this figure is provided by callout number in Table 3-15 on page 34.
3.6.1 TBEN Input Pin
The TBEN input pin can be used as either an enable for the internal timebase/decrementer or as an external
clock input. The mode is controlled by the setting of HID0 bit 19. When this bit is ‘0’, the timebase and decre-
menter update at 1/8th the processor core frequency whenever TBEN is high (traditional enable mode).
When HID0 bit 19 is ‘1’, the timebase and decrementer are clocked by the rising edge of TBEN (external
clock input mode). When the external clock input mode is used, the TBEN input frequency must not exceed
1/16th of the core processor maximum frequency.
Version 2.5
Electrical and Thermal Characteristics
Page 35 of 78
March 26, 2007