欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM25PPC970FX6UB186ET 参数 Datasheet PDF下载

IBM25PPC970FX6UB186ET图片预览
型号: IBM25PPC970FX6UB186ET
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 64-Bit, 1600MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576]
分类和应用: 时钟外围集成电路
文件页数/大小: 78 页 / 3525 K
品牌: IBM [ IBM ]
 浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第28页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第29页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第30页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第31页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第33页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第34页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第35页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第36页  
Datasheet  
PowerPC 970FX RISC Microprocessor  
3.5.1.4 Receive Side Characteristics  
The receive side contains far-end termination circuitry as shown in Figure 3-4 on page 31 for the single-  
ended lines. The total skew from the drive side to the module input pins on the receive side is 350 ps  
(SDS + SPCB) between any two signals (clocks or data). The differential clock termination scheme is shown  
in Figure 3-5 on page 32. All receivers are pseudo-differential with reference to VREF-SSB and with common-  
mode rejection of at least 0.5 × VDD. VREF-SSB can be generated internally by the receive-side circuitry or can  
be derived from the supply voltage.  
Table 3-12. Processor Interconnect SSB Receiver Specifications  
Symbol  
Description  
Minimum  
Typical  
Maximum  
Units  
mV  
%
Notes  
V
SSB reference voltage  
Bus clock duty cycle  
Single-ended terminator  
0.5 × OV  
(V DC + V DC)/2  
REF-SSB  
DD  
OH  
OL  
Bclk  
48  
83  
50  
52  
DC  
TR0  
110  
137  
Ω
110 25%  
Figure 3-5. Differential Clock Termination Circuitry  
OV  
OV  
DD  
DD  
R
R
R
C
C
C
Bclk  
Bclk  
R
C
For high-performance operation, the PI supports the inclusion and operation of receive-side circuitry for clock  
alignment and individual bit-level deskew. An initialization alignment procedure (IAP) is activated at power-on  
reset for bit-level deskew and clock alignment. The IAP uses delay elements in the receive-side circuitry to  
first equalize the delay of the incoming data signals and then center the clock transition in the timing window.  
The timing parameters for the delay elements and flip-flops that register the data signals are summarized  
in Table 3-13 on page 32.  
Table 3-13. Processor Interconnect SSB Timing Parameters for the Deskew and Clock Alignment  
Symbol  
Description  
Bit time  
Minimum  
Typical  
Maximum  
Units  
ns  
Notes  
T
1/(2 × Bclk)  
BIT  
Delay element time  
increment  
T
T
18  
18  
25  
25  
35  
35  
ps  
ps  
Thirty-one delay elements for data  
Sixty-four delay elements for clock  
DED  
DEC  
Delay element time  
increment  
Electrical and Thermal Characteristics  
Page 32 of 78  
Version 2.5  
March 26, 2007