Datasheet
PowerPC 970FX RISC Microprocessor
Table 3-22. Mode Select Type Input Signals
Pin
BUS_CFG(0:2)
CKTERM_DIS
PLL_MULT
Description
Bus configuration
Comment
Pin
AA19, AC19, AB16
AA14
Select processor clock to bus clock ratio.
Disable internal clock receiver terminator.
Clock receiver termination
Select between multiplier 8 or 12
PLL range select
AA8
PLL_RANGE(1:0)
PROCID(0:2)
AA9, AB7
Processor identifier (ID)
For a multiprocessor environment.
L19, M19, M18
Table 3-23. Debug Pins
Pin
Description
Comment
Pin
AVP_RESET
For manufacturing test only.
W23
Disables use of initial alignment procedure
(IAP) to adjust clock skew on the processor
interface.
EI_DISABLE
P20
2
Pull up to OV for debug mode, JTAG - I C
DD
GPULDBG
PPC 970FX debug
AA22
interaction
Version 2.5
Electrical and Thermal Characteristics
Page 39 of 78
March 26, 2007
IBM [ IBM ]
