PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PLL Configuration
The 750 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL con-
figuration signals set the internal CPU and VCO frequency of operation.
PLL Configuration
PLL_CFG
(0:3)
Processor to Bus Frequency Ratio
bin
dec
0
1
0000
Rsv
0001
0010
0011
1
2
3
7.5x
7x
3
PLL Bypass
6
0100
4
2x
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5
6
6.5x
10x
4.5x
3x
7
8
9
5.5x
4x
10
11
12
13
14
15
5x
8x
6x
3.5x
4
Off
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock-off mode, no clocking occurs inside the 750 regardless of the SYSCLK input.
5. The VCO to core clock ratio is 2x for 740/750. This simplifies clock frequency calculations so the user can disregard the VCO frequency. The VCO will
operate correctly when the core clock is within specification.
6. Not tested.
9/6/2002
Version 2.0
Page40
IBM [ IBM ]
