PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
PLL Power Supply Filtering
The AVDD and L2AVdd are power signals provided on the 750 to provide power to the clock generation
phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the
power supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in
Figure 19. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much
noise as possible.
For dd3.2, AVdd is filtered on the module from VDD for the 750 only and can be connected or not, at the
designer’s convenience. For the 750, the L2AVDD must be connected as shown. The 740 requires AVDD to be
supplied as usual.
Figure 19. PLL Power Supply Filter Circuit
10 Ω
V
AV (or L2AV
)
DD
DD
DD
10µF
0.1µF
GND
Decoupling Recommendations
Due to the dynamic power management of the 750, which features large address and data buses, as well as
high operating frequencies, the 750 can generate transient power surges and high frequency noise in its
power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the 750 system, and the 750 itself requires a clean, tightly regulated source of power.
Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with
a low ESR (effective series resistance) rating at each VDD and OVDD pin (and L2OVDD for the 360 CBGA) of
the 750. It is also recommended that these decoupling capacitors receive their power from separate VDD,
OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should range in value from 220pF to 10µF to provide both high- and low-frequency filtering,
and should be placed as close as possible to their associated VDD or OVDD pins. Suggested values for the VDD
pins – 220pF (ceramic), 0.01µF (ceramic), and 0.1µf (ceramic). Suggested values for the OVDD and L2OVDD
pins – 0.01µF (ceramic), 0.1µf (ceramic), and 10µF (tantalum). Only SMT (surface-mount technology) capac-
itors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors – 100µF (tantalum) or 330µF (tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Page 41
Version 2.0
9/6/2002
IBM [ IBM ]
