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IBM25PPC750L-GB500AA2ST 参数 Datasheet PDF下载

IBM25PPC750L-GB500AA2ST图片预览
型号: IBM25PPC750L-GB500AA2ST
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
Spread Spectrum Clock Generator (SSCG)  
When designing with an SSCG, there are a number of issues that must be taken into account.  
An SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750 to function  
correctly with an SSCG, it must be able to accurately track the jitter.  
The accuracy with which the 750 PLL can track the SSCG is referred to as tracking skew. When performing  
system timing analysis, the tracking skew must be added to or subtracted from the I/O timing specifications,  
because the skew appears as a static phase error between the internal PLL and the SSCG.  
To minimize the impact on I/O timing, the following SSCG configuration is recommended:  
• Down-spread mode 0.5% of the maximum frequency  
• Modulation frequency of 30kHz  
• Linear sweep modulation or a modulation profile (Hershey Kiss1) as shown in Figure 3.  
With this configuration, the tracking skew is less than 100 ps.  
Figure 3. Linear Sweep Modulation Profile  
0%  
Down spread  
frequency  
-1%  
0µs  
33.3µs  
Time  
Page 15  
Version 2.0  
9/6/2002  
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