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IBM25PPC750L-GB500AA2ST 参数 Datasheet PDF下载

IBM25PPC750L-GB500AA2ST图片预览
型号: IBM25PPC750L-GB500AA2ST
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
60x Bus Output AC Specifications  
The following table provides the 60x bus output AC timing specifications for the 750 as defined in Figure 6.  
Output timing specification for the L2 bus are provided in the “L2 Bus Output AC Specifications,” on page 23.  
60X Bus Output AC Timing Specifications for the 7501  
2
See ”Recommended Operating Conditions,” on page 11 for operating conditions, C = 50pF  
L
Num  
Characteristic  
All Frequencies  
Unit  
Notes  
Minimum  
Maximum  
12  
13  
14  
SYSCLK to Output Driven (Output Enable Time)  
0.5  
ns  
ns  
ns  
8
5
5
SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST)  
4.5  
5.0  
SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,  
DBB, and TBST)  
15  
16  
SYSCLK to Output Invalid (Output Hold)  
1.0  
ns  
ns  
3, 8, 9  
8
SYSCLK to Output High Impedance (all signals except ABB,  
ARTRY, and DBB)  
6.0  
17  
18  
19  
20  
21  
SYSCLK to ABB and DBB high impedance after precharge  
SYSCLK to ARTRY high impedance before precharge  
SYSCLK to ARTRY precharge enable  
1.0  
5.5  
tSYSCLK  
ns  
4, 6, 8  
8
0.2×tSYSCLK + 1.0  
ns  
3, 4, 7  
4, 7  
Maximum delay to ARTRY precharge  
1
2
tSYSCLK  
tSYSCLK  
SYSCLK to ARTRY high impedance after precharge  
4, 7, 8  
Note:  
1. All output specifications are measured from Vm of the rising edge of SYSCLK to Vm of the signal in question. Both input and output timings are mea-  
sured at the pin.  
2. All maximum timing specifications assume CL = 50pF.  
3. This minimum parameter assumes CL = 0pF.  
4. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of  
SYSCLK to compute the actual time duration of the parameter in question.  
5. This footnote has been deleted.  
6. Nominal precharge width for ABB and DBB is 0.5 tSYSCLK  
7. Nominal precharge width for ARTRY is 1.0 tSYSCLK  
.
.
8. Guaranteed by design and characterization, and not tested.  
9. Connecting L2_TSTCLK to GND no longer provides additional Output Hold. For new designs, L2_TSTCLK should be pulled up to OVDD, but it can be  
left connected to GND in Legacy systems.  
9/6/2002  
Version 2.0  
Page18  
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