欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM25PPC750L-EB0C366W 参数 Datasheet PDF下载

IBM25PPC750L-EB0C366W图片预览
型号: IBM25PPC750L-EB0C366W
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 366MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 46 页 / 610 K
品牌: IBM [ IBM ]
 浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第31页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第32页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第33页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第34页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第36页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第37页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第38页浏览型号IBM25PPC750L-EB0C366W的Datasheet PDF文件第39页  
PowerPC 750 SCM RISC Microprocessor  
PID8p-750  
Preliminary Copy  
PLL Power Supply Filtering  
The L2AVDD power signal on the PID8p-750, provides power to the L2 cache delay-locked loop. To ensure  
stability of the internal clock, the power supplied to the L2AVDD input signal should be filtered using a circuit  
similar to the one shown in Figure 16. This circuit should be placed as close as possible to the L2AVDD pin to  
ensure it filters out as much noise as possible. For consistency in L2AVDD noise measurements, the scope  
probe must be placed as close to the BGA pin as possible and pulse widths less than 10ns may be ignored.  
Figure 16. PLL Power Supply Filter Circuit  
10 Ω  
VDD  
L2AVDD  
10µF  
0.1µF  
GND  
Decoupling Recommendations  
Due to the PID8p-750’s dynamic power management feature, large address and data buses, and high oper-  
ating frequencies, the PID8p-750 can generate transient power surges and high frequency noise in its power  
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other  
components in the PID8p-750 system, and the PID8p-750 itself requires a clean, tightly regulated source of  
power. Therefore, it is strongly recommended that the system designer place at least one decoupling capaci-  
tor with a low ESR (effective series resistance) rating at each VDD and OVDD pin (and L2OVDD for the 360  
CBGA) of the PID8p-750. It is also recommended that these decoupling capacitors receive their power from  
separate VDD, OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.  
These capacitors should range in value from 220pF to 10µF to provide both high and low- frequency filtering,  
and should be placed as close as possible to their associated VDD or OVDD pins. Suggested values for the VDD  
pins – 220pF (ceramic), 0.01µF (ceramic), and 0.1µf (ceramic). Suggested values for the OVDD pins – 0.01µF  
(ceramic), 0.1µf (ceramic), and 10µF (tantalum). Only SMT (surface-mount technology) capacitors should be  
used to minimize lead inductance.  
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-  
ing the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors  
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.  
They should also be connected to the power and ground planes through two vias to minimize inductance.  
Suggested bulk capacitors – 100µF (AVX TPS tantalum) or 330µF (AVX TPS tantalum).  
Connection Recommendations  
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal  
level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to GND.  
All NC (no-connect) signals must remain unconnected.  
Power and ground connections must be made to all external VDD, OVDD, and GND, pins of the PID8p-750.  
External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all  
SRAMs and at the L2SYNC_IN input of the PID8p-750. The L2CLKOUTA network could be used only, or the  
9/30/99  
Version 2.0  
Datasheet  
Page 31  
 
 复制成功!