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IBM25PPC750GXECB5083T 参数 Datasheet PDF下载

IBM25PPC750GXECB5083T图片预览
型号: IBM25PPC750GXECB5083T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 1054 K
品牌: IBM [ IBM ]
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Datasheet  
IBM PowerPC 750GX RISC Microprocessor  
DD1.X  
List of Figures  
Figure 2-1. IBM PowerPC 750GX RISC Microprocessor Block Diagram ................................................. 13  
Figure 3-1. SYSCLK Input Timing Diagram .............................................................................................. 18  
Figure 3-2. Linear Sweep Modulation Profile ........................................................................................... 19  
Figure 3-3. Input Timing Definition ........................................................................................................... 21  
Figure 3-4. Input Timing Diagram ............................................................................................................. 21  
Figure 3-5. Mode Select Input Timing Diagram ........................................................................................ 22  
Figure 3-6. Output Valid Timing Definition ................................................................................................ 24  
Figure 3-7. Output Timing Diagram for IBM PowerPC 750GX RISC Microprocessor .............................. 25  
Figure 3-8. JTAG Clock Input Timing Diagram ......................................................................................... 27  
Figure 3-9. TRST Timing Diagram ........................................................................................................... 27  
Figure 3-10. Boundary-Scan Timing Diagram ............................................................................................ 27  
Figure 3-11. Test Access Port Timing Diagram .......................................................................................... 28  
Figure 4-1. Mechanical Dimensions, Standard Package .......................................................................... 31  
Figure 4-2. Mechanical Dimensions, ROHS-Compatible Package .......................................................... 33  
Figure 4-3. Module Substrate Decoupling Voltage Assignments ............................................................. 35  
Figure 4-4. PowerPC 750GX Microprocessor Ball Placement ................................................................. 36  
Figure 5-1. Single PLL Power Supply Filter Circuit with A1VDD Pin and A2VDD Pin Tied to GND ......... 51  
Figure 5-2. PLL Power Supply Filter Circuit with Two AVDD Pins and One Ferrite Bead ........................ 51  
Figure 5-3. Dual PLL Power Supply Filter Circuits ................................................................................... 52  
Figure 5-4. Orientation and Layout of the 750GX Decoupling Capacitors ............................................... 54  
Figure 5-5. Driver Impedance Measurement ............................................................................................ 55  
Figure 5-6. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector ........................ 61  
Figure 5-7. Package Exploded Cross-Sectional View with Several Heat-Sink Options ........................... 62  
Figure 5-8. C4 Package with Heat Sink Mounted to a Printed-Circuit Board ........................................... 65  
Figure 5-9. Thermal Performance of Select Thermal Interface Material .................................................. 66  
Figure 5-10. Example of a Pin-Fin Heat-Sink-to-Ambient Thermal Resistance versus Airflow Velocity .... 68  
750GX_dsLOF.fm SA14-2765-02  
September 2, 2005  
List of Figures  
Page 5 of 73