Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
List of Figures ................................................................................................................ 5
List of Tables .................................................................................................................. 7
1. General Information .................................................................................................... 9
1.1 Features ............................................................................................................................................ 9
1.2 Design Highlights ............................................................................................................................ 11
1.3 Processor Version Register ............................................................................................................ 11
1.4 Part Number Information ................................................................................................................. 12
2. Overview .................................................................................................................... 13
2.1 Block Diagram ................................................................................................................................. 13
2.2 General Parameters ........................................................................................................................ 14
3. Electrical and Thermal Characteristics ................................................................... 15
3.1 DC Electrical Characteristics ........................................................................................................... 15
3.2 AC Electrical Characteristics ........................................................................................................... 17
3.3 Clock AC Specifications .................................................................................................................. 18
3.4 Spread Spectrum Clock Generator ................................................................................................. 19
3.4.1 Design Considerations .......................................................................................................... 19
3.5 60x Bus Input AC Specifications ..................................................................................................... 20
3.5.1 Input Setup Timing ................................................................................................................ 20
3.6 60x Bus Output AC Specifications .................................................................................................. 23
3.6.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 26
4. Dimensions and Signal Assignments ..................................................................... 29
4.1 Package .......................................................................................................................................... 29
4.1.1 Reduced-Lead package ........................................................................................................ 29
4.1.1.1 Mechanical Specifications .............................................................................................. 29
4.1.1.2 Assembly Considerations ............................................................................................... 29
4.1.1.3 Board Layout Considerations ......................................................................................... 30
4.2 Module Substrate Decoupling Voltage Assignments ...................................................................... 35
4.3 Microprocessor Ball Placement ....................................................................................................... 36
4.4 Pinout Listings ................................................................................................................................. 37
5. System Design Information ..................................................................................... 46
5.1 Core Voltage Operation .................................................................................................................. 46
5.2 Low Voltage Operation at Lower Frequency ................................................................................... 46
5.2.1 Overview ................................................................................................................................ 46
5.2.2 Restrictions and Considerations for PLL Configuration ......................................................... 47
5.2.2.1 Configuration Restriction on Frequency Transitions ...................................................... 47
5.2.3 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................ 48
5.2.4 PLL Configuration .................................................................................................................. 48
5.3 PLL Power Supply Filtering ............................................................................................................. 50
5.4 Decoupling Recommendations ....................................................................................................... 52
5.5 Connection Recommendations ....................................................................................................... 54
750GX_dsTOC.fm SA14-2765-02
September 2, 2005
Page 3 of 73
IBM [ IBM ]
