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IBM25PPC750GXECB5083T 参数 Datasheet PDF下载

IBM25PPC750GXECB5083T图片预览
型号: IBM25PPC750GXECB5083T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 1054 K
品牌: IBM [ IBM ]
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Datasheet  
IBM PowerPC 750GX RISC Microprocessor  
DD1.X  
1. General Information  
The IBM PowerPC® 750GX RISC1 Microprocessor is a 32-bit implementation of the IBM PowerPC family.  
This document contains pertinent physical and electrical characteristics of the IBM PowerPC 750GX RISC  
Microprocessor Revision DD1.X Single Chip Module (SCM). The IBM PowerPC 750GX RISC Microprocessor  
is also referred to as the 750GX throughout this document.  
1.1 Features  
This section summarizes the features of the 750GX  
implementation of the PowerPC Architecture™.  
Major features of the 750GX include the following:  
• Dispatch unit  
– Full hardware detection of dependencies  
(resolved in the execution units)  
– Dispatch two instructions to six independent  
units (system, branch, load/store, fixed-point  
unit 1, fixed-point unit 2, or floating-point)  
– 4-stage pipeline: fetch, dispatch, execute,  
and complete  
• Branch processing unit  
– Four instructions fetched per clock  
– One branch processed per cycle (plus  
resolving two speculations)  
– Up to one speculative stream in execution,  
one additional speculative stream in fetch  
– 512-entry branch history table (BHT) for  
dynamic prediction  
– Serialization control (predispatch,  
postdispatch, execution, serialization)  
• Fixed-point units  
– 64-entry, 4-way set associative branch  
target instruction cache (BTIC) for  
eliminating branch delay slots  
– Fixed-point unit 1 (FXU1): multiply, divide,  
shift, rotate, arithmetic, logical  
– Fixed-point unit 2 (FXU2): shift, rotate,  
arithmetic, logical  
– Single-cycle arithmetic: shift, rotate, logical  
– Multiply and divide support (multi-cycle)  
– Early out multiply  
• Decode  
– Register file access  
– Forwarding control  
– Partial instruction decode  
– Thirty-two 32-bit general purpose registers  
• Load/store unit  
• Floating-point unit  
– One cycle load or store cache access (byte,  
half-word, word, double-word)  
– Effective address generation  
– Hits under miss (four outstanding misses)  
– Single-cycle misaligned access within  
double-word boundary  
– Alignment, zero padding, sign extend for  
integer register file  
– Floating-point internal format conversion  
(alignment, normalization)  
– Sequencing for load/store multiples and  
string operations  
– Store gathering  
– Cache and translation lookaside buffer  
(TLB) instructions  
– Big-endian and little-endian byte addressing  
supported  
– Support for IEEE®-754 standard single-pre-  
cision and double-precision floating-point  
arithmetic  
– Optimized for single-precision multiply/add  
– Thirty-two 64-bit floating-point registers  
– Enhanced reciprocal estimates  
– 3-cycle latency, 1-cycle throughput,  
single-precision multiply-add  
– 3-cycle latency, 1-cycle throughput,  
double-precision add  
– 4-cycle latency, 2-cycle throughput,  
double-precision multiply-add  
– Hardware support for divide  
– Hardware support for denormalized  
numbers  
– Time deterministic non-IEEE mode  
– Misaligned little-endian support in hardware  
1. Reduced instruction set computer  
750GX_ds_body.fm.SA14-2765-02  
September 2, 2005  
General Information  
Page 9 of 73