Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Table 4-3. Signal Listing for the CBGA Package (Continued)
Signal Name
INT
Pin Count
1
Active
Low
Input/Output
Input
Notes
I/O voltage mode select for 60x bus.
L1_TSTCLK
L2_TSTCLK
1
1
1
High
High
Low
Input
Input
Input
See Section 5.9.3 on page 70 for setup conditions.
These are test signals for factory use only and must
be pulled up to OV for normal machine operation.
DD
These are test signals for factory use only and must
LSSD_MODE
MCP
be pulled up to OV for normal machine operation.
DD
1
32
5
2
1
1
1
1
1
1
1
1
1
1
1
1
1
Low
—
Input
—
OV
Supply for receivers/drivers
See notes 1 and 2.
DD
PLL_CFG[0:4]
PLL_RNG[0:1]
QACK
QREQ
RSRV
SMI
High
High
Low
Low
Low
Low
Low
High
Low
High
Low
High
High
High
Low
Input
Input
Input
Output
Output
Input
SRESET
SYSCLK
TA
Input
Input
Input
TBEN
Input
TBST
Input/Output
Input
TCK
TDI
Input
TDO
Output
Input
TEA
Optional: 64/32-Bit Data Bus mode select.
This function will be set when HRESET transitions
(low to high).
TLBISYNC
1
Low
Input
TLBISYNC: high = 64-bit mode, low = 32-bit mode.
TMS
TRST
TS
1
1
High
Low
Low
High
High
Input
Input
1
Input/Output
Output
TSIZ[0:2]
TT[0:4]
3
5
Input/Output
V
32
Supply for core
DD
Notes:
1. QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-charge mode in the
750GX.
QACK in a logical low state at the transition of HRESET from asserted to negated enables extended pre-charge mode in the
750GX.
2. QACK, in a logical low state at the transition of QREQ from asserted to negated, enables the 750GX processor to enter the soft
stop (Nap) state for proper JTAG emulator operation.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
Dimensions and Signal Assignments
Page 41 of 73
IBM [ IBM ]
