Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Table 4-3. Signal Listing for the CBGA Package
Signal Name
A[0:31]
Pin Count
Active
High
—
Input/Output
Input/Output
—
Notes
32
1
A1V
A2V
Supply for PLL0
Supply for PLL1
DD
DD
1
—
—
AACK
ABB
1
Low
Low
—
Input
1
Input/Output
—
AGND
AP[0:3]
ARTRY
BG
1
Ground for PLL
4
High
Low
Low
Low
Input/Output
Input/Output
Input
1
1
BR
1
Output
I/O voltage mode select for 60x bus.
BVSEL
1
High
Input
See Section 5.9.3 on page 70 for setup conditions.
CI
1
1
1
1
1
Low
Low
Low
High
Low
Output
Input
CKSTP_IN
CKSTP_OUT
CLK_OUT
DBB
Output
Output
Input/Output
Factory usage mode pin. Pull inactive (high) when
HRESET transitions from low to high for normal
machine operation.
DBDIS
DBG
1
1
1
Low
Low
Low
Input
Input
Input
Factory usage mode pin. Pull inactive (high) when
HRESET transitions from low to high for normal
machine operation.
DBWO
DH[0:31]
DL[0:31]
DP[0:31]
32
32
8
High
High
High
Input/Output
Input/Output
Input/Output
Optional data retry mode select. This function will be
set when HRESET transitions from low to high.
DRTRY
1
Low
Input
DRTRY high indicates data-retry mode; DRTRY low
indicates no data-retry mode.
GBL
1
60
1
Low
—
Input/Output
Ground
HRESET
—
Common ground
See note 1.
Low
Input
Notes:
1. QACK in a logical high state at the transition of HRESET from asserted to negated enables standard pre-charge mode in the
750GX.
QACK in a logical low state at the transition of HRESET from asserted to negated enables extended pre-charge mode in the
750GX.
2. QACK, in a logical low state at the transition of QREQ from asserted to negated, enables the 750GX processor to enter the soft
stop (Nap) state for proper JTAG emulator operation.
Dimensions and Signal Assignments
Page 40 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
