Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Table 4-2. Pinout Listing for the CBGA package (Continued)
Signal Name
Pin Number
D14, B17, B14, A15, B13
Active
High
Input/Output
Input/Output
Notes
2
TT[0:4]
C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, J13, K3,
K8, K11, K13, K18, L3, L8, L11, L13, L18, M8, M9,
M13, R6, R9, R12, R15, T8, T13, V10, V11
V
—
—
DD
WT
U5
Low
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal machine operation.
DD
2. OV inputs supply power to the input/output drivers and V inputs supply power to the processor core.
DD
DD
3. These pins are reserved for potential future use.
4. BVSEL and L1_TSTCLK select the input/output voltage mode on the 60x bus.
5. TCK must be tied high or low for normal machine operation.
6. Address and data parity should be left floating if unused in the design.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
Dimensions and Signal Assignments
Page 39 of 73
IBM [ IBM ]
