Preliminary
PowerPC 750FL RISC Microprocessor
List of Figures
Figure 1-1. Part Number Legend .............................................................................................................. 13
Figure 2-1. PowerPC 750FL RISC Microprocessor Block Diagram ......................................................... 14
Figure 3-1. SYSCLK Input Timing Diagram .............................................................................................. 20
Figure 3-2. Linear Sweep Modulation Profile ........................................................................................... 21
Figure 3-3. Input Timing Diagram ............................................................................................................. 22
Figure 3-4. Mode Select Input Timing Diagram ........................................................................................ 23
Figure 3-5. Output Valid Timing Definition ................................................................................................ 25
Figure 3-6. Output Timing Diagram for PowerPC 750FL RISC Microprocessor ...................................... 26
Figure 3-7. JTAG Clock Input Timing Diagram ......................................................................................... 27
Figure 3-8. TRST Timing Diagram ........................................................................................................... 28
Figure 3-9. Boundary-Scan Timing Diagram ............................................................................................ 28
Figure 3-10. Test Access Port Timing Diagram .......................................................................................... 28
Figure 4-1. Module Substrate Decoupling Voltage Assignments ............................................................. 29
Figure 4-2. Mechanical Dimensions and Bottom Surface Nomenclature of the Reduced Lead CBGA
Package ................................................................................................................................. 30
Figure 4-3. PowerPC 750FL Microprocessor Ball Placement .................................................................. 31
Figure 5-1. Single PLL Power Supply Filter Circuit with A1VDD Pin and A2VDD Pin Tied to GND ......... 43
Figure 5-2. PLL Power Supply Filter Circuit with Two AVDD Pins and One Ferrite ................................. 44
Figure 5-3. Dual PLL Power Supply Filter Circuits ................................................................................... 45
Figure 5-4. 750FL Microprocessor Pin Locations: OV , V , GND, and Signal Pins ............................ 47
DD
DD
Figure 5-5. Orientation and Layout of the 750FL Microprocessor Decoupling Capacitors ....................... 48
Figure 5-6. Driver Impedance Measurement ............................................................................................ 49
Figure 5-7. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector ........................ 55
Figure 5-8. Thermalloy #2328B Pin-Fin Heat Sink-to-Ambient Thermal Resistance Versus Airflow
Velocity ................................................................................................................................... 58
Figure 5-9. C4 Package with Heat Sink Mounted to a Printed Circuit Board ........................................... 59
Figure 5-10. Exploded Cross-Sectional View of Package with Several Heat Sink Options ....................... 61
Figure 5-11. Thermal Performance of Select Thermal Interface Materials ................................................. 62
750flds60LOF.fm.6.0
April 27, 2007
List of Figures
Page 5 of 65
IBM [ IBM ]
