Preliminary
PowerPC 750FL RISC Microprocessor
1. General Information
The IBM® PowerPC® 750FL RISC microprocessor is a 32-bit implementation of the IBM PowerPC family of
reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and
electrical characteristics of the IBM PowerPC 750FL. The PowerPC 750FL die, functionality, timing, ac and
dc electrical specifications, mechanical specifications, and errata are identical to those of the PowerPC
750FX DD2.3. The only differences from the PowerPC 750FX are in the part number, application conditions,
speed grade, power dissipation, and consumer grade reliability. The PowerPC 750FL is available only in a
restriction of hazardous substances (RoHS) compatible, reduced-lead package.
1.1 Features
This section summarizes the features of the 750FL microprocessor implementation of the PowerPC Architec-
ture
™
. Major features of the 750FL microprocessor include the following features:
• Branch processing unit
– Four instructions fetched per clock
– One branch processed per cycle (plus resolving two speculations)
– Up to one speculative stream in execution and one additional speculative stream in fetch
– 512-entry branch history table (BHT) for dynamic prediction
– 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay
slots
• Decode
– Register file access
– Forwarding control
– Partial instruction decode
• Load/store unit
– One cycle load or store cache access (byte, half-word, word, double-word)
– Effective address generation
– Hits under miss (one outstanding miss)
– Single-cycle misaligned access within double-word boundary
– Alignment, zero padding, sign extend for integer register file
– Floating-point internal format conversion (alignment, normalization)
– Sequencing for load/store multiples and string operations
– Store gathering
– Cache and translation lookaside buffer (TLB) instructions
– Big- and little-endian byte addressing supported
– Misaligned little-endian support in hardware
• Dispatch unit
– Full hardware detection of dependencies (resolved in the execution units)
– Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit
(FXU) 1, FXU2, or floating-point)
– Four-stage pipeline: fetch, dispatch, execute, and complete
– Serialization control (predispatch, postdispatch, execution, serialization)
• Fixed-point units
– FXU1: multiply, divide, shift, rotate, arithmetic, logical
– FXU2: shift, rotate, arithmetic, logical
– Single-cycle arithmetic, shift, rotate, logical
– Multiply and divide support (multicycle)
750flds60.fm.6.0
April 27, 2007
General Information
Page 9 of 65
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