PowerPC 750FL RISC Microprocessor
Preliminary
3.2 Clock ac Specifications
Table 3-7 provides the clock ac timing specifications as defined in Figure 3-1.
Table 3-7. Clock ac Timing Specifications 1, 6, 7
Value
Minimum Maximum
Number
(Timing Reference)
Characteristic
Unit
Notes
1, 6
Processor frequency
400
20
733
200
50
MHz
MHz
ns
SYSCLK frequency
1
2, 3
SYSCLK cycle time
5.0
1.0
25
SYSCLK rise and fall slew rate
SYSCLK duty cycle measured at 0.8 V
Measurement Reference Voltage for SYSCLK (all I/O voltages)
SYSCLK cycle-to-cycle jitter
Internal PLL relock time
V/ns
%
3
3
4
75
VMSYSCLK
0.65
V
–
–
150
100
ps
4, 3
5
μs
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, processor (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Table 5-2 750FL Microprocessor PLL Configuration on page 40
for valid PLL_CFG[0:4] settings.
2. The SYSCLK slew rate applies between 0.4 V and 1.0 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. See Section 3.3 Spread Spectrum Clock Generator on page 21 for long term jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also
applies when the PLL has been disabled and subsequently reenabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.
6. This is a statement of the capability of the 750FL I/O circuitry. Not all systems can run at the maximum SYSCLK frequency. Contact
IBM PowerPC Application Engineering for more information on high-speed bus design.
7. See Table 3-2 Recommended Operating Conditions on page 17 for recommended operating conditions
Figure 3-1. SYSCLK Input Timing Diagram
1
2
3
4
4
CVIH
VM
SYSCLK
CVIL
VMSYSCLK - Midpoint Voltage for SYSCLK
Electrical and Thermal Characteristics
Page 20 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
