PowerPC 750FL RISC Microprocessor
Preliminary
3.4 60x Bus Input ac Specifications
Table 3-8. 60x Bus Input Timing Specifications 1, 5, 7
1.8 V Mode
2.5 V Mode
3.3 V Mode
Number
Characteristic
Unit
ns
Notes
Minimum Maximum Minimum Maximum Minimum Maximum
10a All inputs valid to SYSCLK (input setup)
1.0
1.5
1.5
1.5
1.8
1.8
INT_, SMI_, MCP, TBEN, DRTRY, and
TLBISYNC (input setup)
10b
Mode select input setup to HRESET
(TLBISYNC, DRTRY)
10c
8
8
8
tSYSCLK 2, 3, 4, 5
11a SYSCLK to inputs invalid (input hold)
0.65
1.5
0.65
2.5
0.55
2.5
ns
ns
6
INT_, SMI_, MCP, TBEN, DRTRY, and
11b
TLBISYNC (input hold)
HRESET to mode select input hold
(TLBISYNC, DRTRY)
11c
0
0
0
ns
2, 4, 5
Measurement Reference Voltage for
Inputs
VM
OVDD/2
Notes:
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
SYSCLK. Input and output timings are measured at the pin (see Figure 3-3).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-4 Mode Select Input Timing Diagram on
page 23).
3. tSYSCLK, is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK in ns to compute the actual time duration (in ns) of the parameter in question.
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
6. See Alternate I/O Timing for 3.3 V Bus on page 26.
7. See Table 3-2 Recommended Operating Conditions on page 17 for operating conditions.
Figure 3-3 provides the input timing diagram for the 750FL microprocessor.
Figure 3-3. Input Timing Diagram
VMsysclk(0.65V)
SYSCLK
10a
10b
11a
11b
ALL INPUTS
VM
VM
VM = Midpoint Voltage (OVDD/2)
Electrical and Thermal Characteristics
Page 22 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
