Preliminary
PowerPC 750FL RISC Microprocessor
Table 5-2. 750FL Microprocessor PLL Configuration (Sheet 2 of 2)
PLL_CFG [0:4]
Processor to Bus Frequency Ratio (PBFR)
Binary
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Decimal
15
7.5×
8×
16
17
8.5×
9×
18
19
9.5×
10×
11×
12×
13×
14×
15×
16×
17×
18×
19×
20×
Off3
20
21
22
23
24
25
26
27
28
29
30
31
Notes:
1. The 2×−2.5× processor to bus ratios are not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for manufacturing use only.
The ac timing specifications given in the document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 750FL microprocessor regardless of the SYSCLK input.
750flds60.fm.6.0
April 27, 2007
System Design Information
Page 41 of 65
IBM [ IBM ]
