Preliminary
PowerPC 750FL RISC Microprocessor
After both PLLs are running and locked, the processor frequency can be toggled with very low latency. For
example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock.
HID1[PS] can be reset to 0, causing the processor clock source to make the transition from PLL1 back to
PLL0. If PLL0 is not needed for some time, it can be configured to be off while not in use. This is done by
resetting the HID1[PC0] field to 0, and setting HID1[PI0] to 1. Turning the nonselected PLL off results in a
modest power savings, but introduces added latency when changing frequency. If PLL0 is configured to be
off, the procedure for switching to PLL0 as the selected PLL involves changing the configuration and range
bits, waiting for lock, and then selecting PLL0, as described in the previous paragraph.
5.1.1 Restrictions and Considerations for PLL Configuration
Avoid the following when reconfiguring the PLLs:
1. The configuration and range bits in HID1 must only be modified for the nonselected PLL because it
requires time to lock before it can be used as the source for the processor clock.
2. The HID1[PI0] bit can only be modified when PLL0 is not selected.
3. Whenever one of the PLLs is reconfigured, it must not be selected as the active PLL until enough time
has elapsed for the PLL to lock.
4. At all times, the frequency of the processor clock, as determined by the various configuration settings,
must be within the specification range for the current operating conditions.
5. Never select a PLL that is in the off configuration.
5.1.1.1 Configuration Restriction on Frequency Transitions
It is considered a programming error to switch from one PLL to the other when both are configured in a
half-cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (cfg = ‘01001’) and PLL1 config-
ured in 13:2 mode (cfg = ‘01101’), changing the select bit (HID1[PS]) is not allowed. In cases where such a
pairing of configurations is required, an intermediate full-cycle configuration must be used between the two
half-cycle modes. For example, with PLL0 at 9:2, configure and select PLL1 to 6:1 mode, then reconfigure
PLL0 to 13:2 mode, and select it when it locks.
750flds60.fm.6.0
April 27, 2007
System Design Information
Page 39 of 65
IBM [ IBM ]
