PowerPC 750FL RISC Microprocessor
Preliminary
5. System Design Information
This section provides electrical and thermal design recommendations for the successful application of the
750FL microprocessor. For more information, see the IBM PowerPC 750L/CXe/FX/GX Microprocessor
Frequently Asked Questions, the IBM PowerPC 750FX and 750FL RISC Microprocessor Errata List DD2.X,
any applicable PCNs, and the other PowerPC documentation and application notes in the PowerPC Tech-
nical Library at http://www.ibm.com/chips/techlib/
5.1 PLL Considerations
The 750FL design includes two phase-locked loops (PLLs), PLL0 and PLL1, allowing the processor clock
frequency to dynamically change between the PLL frequencies through software control. Use the bits in the
HID1 register to specify the following settings:
1. The frequency range of each PLL
2. The clock multiplier for each PLL
3. External or internal control of PLL0
4. Which PLL is selected as the source of the processor clock.
For HID1 bit definitions, see the IBM PowerPC 750FX and 750FL RISC Microprocessor User’s Manual.
At power-on reset, the HID1 register contains zeros for all the non-read-only bits (bits 7 − 31). This configura-
tion corresponds to the selection of PLL0 as the source of the processor clocks and selects the external
configuration and range pins to control PLL0. The external configuration and range pin values are accessible
to software using HID1 read-only bits 0 − 6. PLL1 is always controlled by its internal configuration and range
bits. The HID1 setting associated with hard reset corresponds to a PLL1 configuration of clock off, and selec-
tion of the medium frequency range.
HRESET must be asserted during power up long enough for the PLLs to lock and for the internal hardware to
be reset. When this timing is satisfied, HRESET can be negated. The processor then proceeds to execute
instructions, clocked by PLL0 as configured through the external pins. The processor clock frequency can be
modified from this initial setting in one of two ways. First, as with earlier designs, HRESET can be asserted,
and the external configuration pins can be set to a new value. The machine state is reset in this process, and,
as always, HRESET must be held asserted while the PLL relocks, and the internal state is reset. Second, the
introduction of another PLL provides an alternative means of changing the processor clock frequency, which
does not involve the loss of machine state nor a delay for PLL relock.
The following sequence can be used to change processor clock frequency:
Note: Assume PLL0 is currently the source for the processor clock.
1. Configure PLL1 to produce the required clock frequency by setting HID1[PR1] and HID1[PC1] to the
appropriate values.
2. Wait for PLL1 to lock. The lock time is the same for both PLLs and is provided in the hardware specifica-
tion.
3. Set HID1[PS] to 1 to initiate the transition from PLL0 to PLL1 as the source of the processor clocks.
From the time the HID1 register is updated to select the new PLL, the transition to the new clock fre-
quency is completed within three bus cycles. After the transition, the HID(PSS) bit indicates which PLL is
in use.
System Design Information
Page 38 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
