PowerPC 750FL RISC Microprocessor
Preliminary
1.2 Design Level Considerations and Features
The 750FL microprocessor supports several unique features including those in the following list. The IBM
application note Differences between the PowerPC 750FX, 750, 750CX, and 750CXe Microprocessors
provides a more detailed explanation of these features.
• Incorporates an on-chip, 512 KB, two-way, set-associative L2 cache
• Provides a 64- or 32-bit data bus mode, selectable through the TLBISYNC pin
• Supports 1.8 V, 2.5 V, or 3.3 V I/O modes
• Includes all 60x bus pins on earlier PowerPC 750 designs and additional signals
• Enhanced 60x bus supports pipelined consecutive read transactions and higher frequency operation
• Dual PLLs for additional power savings capabilities
• Four additional IBAT/DBAT registers
• New ceramic ball grid array (CBGA) package with additional pins and depopulated footprint
1.3 Processor Version Register
The 750FL microprocessor has the following Processor Version Register (PVR) values for the respective
design revision levels. The initial release of the 750FL microprocessor is DD2.3.
The 750FL PVR is x“7000”. This is identical to the PVR value of the 750FX.
Table 1-1. 750FL Microprocessor PVR
750FL Microprocessor Design Revision Level
DD2.3
750FL Microprocessor PVR
x‘700a 02b3’
Notes:
1. Nibbles shown as ‘b’ are to be ignored, and are for factory use only. Nibbles shown as ‘a’ can be ‘0’ or ‘1’.
2. If L2_TSTCLK is pulled low, the PVR might read x‘0008 02b_’. L2TSTCLK must be pulled up for normal operation.
General Information
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750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
