PowerPC 750FL RISC Microprocessor
Preliminary
– Early-out multiply
– Thirty-two 32-bit general purpose registers
• Floating-point unit
– Support for IEEE-754 standard single- and double-precision floating-point arithmetic
– Optimized for single-precision multiply and add
– Thirty-two, 64-bit floating point registers
– Enhanced reciprocal estimates
– Three-cycle latency, 1-cycle throughput, single-precision multiply-add
– Three-cycle latency, 1-cycle throughput, double-precision add
– Four-cycle latency, 2-cycle throughput, double-precision multiply-add
– Hardware support for divide
– Hardware support for denormalized numbers
– Time deterministic non-IEEE mode
• System unit
– Executes CR logical instructions and miscellaneous system instructions
– Special register transfer instructions
• Level 1 (L1) Cache structure
– 32 KB, 32-byte line, 8-way set associative instruction cache
– 32 KB, 32-byte line, 8-way set associative data cache
– Single-cycle cache access
– Pseudo-LRU replacement
– Copy-back or write-through data cache (on a page per page basis)
– Parity on L1 tags and arrays
– Three-state modified, exclusive, invalid (MEI) memory coherency
– Hardware support for data coherency
– Nonblocking instruction cache (one outstanding miss)
– Nonblocking data cache (two outstanding misses)
– No snooping of instruction cache
• Memory management unit
– 64 entry, 2-way set associative instruction TLB (total 128)
– 64 entry, 2-way set associative data TLB (total 128)
– Hardware reload for TLBs
– Eight instruction block address translators (BATs) and 8 data BATs
52
– Virtual storage support for up to 4 exabytes (2 ) virtual storage
32
– Real memory support for up to 4 GB (2 ) of physical memory
– Support for big- and little-endian addressing
• Dual PLLs
– Allows seamless frequency switching
• Level 2 (L2) cache
– Internal L2 cache controller and 4096 entry tags: 512 KB data SRAMs
– Two-way set-associative, supports locking by way
– Copy-back or write-through data cache on a page basis, or for all L2
– 64-byte sectored line size
– L2 frequency at core speed
– ECC protection on SRAM array
– Parity on L2 tags
– Supports up to two outstanding misses
(one data and one instruction, or two data)
General Information
Page 10 of 65
750flds60.fm.6.0
April 27, 2007
IBM [ IBM ]
