DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
Table 4-1. Pinout Listing for the CBGA package (Continued)
Signal Name
TSIZ[0:2]
TT[0:4]
Pin Number
Active
High
Input/Output
Output
Notes
A14, B12, B11
D14, B17, B14, A15, B13
High
Input/Output
C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, J13, K3,
K8, K11, K13, K18, L3, L8, L11, L13, L18, M8, M9,
M13, R6, R9, R12, R15, T8, T13, V10, V11
V
—
—
2
DD
WT
U5
Low
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal machine operation.
DD
2. OV inputs supply power to the Input/Output drivers and V inputs supply power to the processor core.
DD
DD
3. These pins are reserved for potential future use.
4. BVSEL and L1_TSTCLK select the Input/Output voltage mode on the 60x bus (see Section 5.7 on page 49).
5. TCK must be tied high or low for normal machine operation.
6. Address and data parity should be left floating if unused in the design.
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
4. Dimensions and Signal Assignments
Page 27 of 63
IBM [ IBM ]
