DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
.
Table 4-2. Signal Locations
Signal
A0
Ball Location
E20
Signal
DH0
Ball Location
W18
T17
Signal
DL0
Ball Location
A2
Signal
Ball Location
AACK
ABB
A8
A1
E19
D20
C20
D19
C19
A20
E16
B20
E17
B18
A18
A17
A19
A16
B16
B10
B9
DH1
DL1
A1
C2
E4
C1
E2
D2
E1
D1
F1
G2
F2
H2
H4
G1
K2
J2
Y6
A2
DH2
Y20
Y19
W20
V19
U19
T16
DL2
AGND
ARTRY
BG
Y14
W7
W4
Y3
A3
DH3
DL3
A4
DH4
DL4
A5
DH5
DL5
BR
A6
DH6
DL6
BVSEL
W9
Y12
T4
A7
DH7
DL7
CHECKSTOP (CKSTP_OUT)
CI
A8
DH8
T19
DL8
A9
DH9
U20
V20
R19
N17
P17
R20
P20
N20
P19
M20
L20
DL9
CLK_OUT
CKSTP (CKSTP_IN)
DBB
T5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
DH10
DH11
DH12
DH13
DH14
DH15
DH16
DH17
DH18
DH19
DH20
DH21
DH22
DH23
DH24
DH25
DH26
DH27
DH28
DH29
DH30
DH31
DL10
DL11
DL12
DL13
DL14
DL15
DL16
DL17
DL18
DL19
DL20
DL21
DL22
DL23
DL24
DL25
DL26
DL27
DL28
DL29
DL30
DL31
Y10
U7
DBDIS
A10
Y5
DBG
DBWO
A6
DRTRY
W3
W1
Y11
Y9
GBL
K1
J1
HRESET
INT
A9
B7
L2
L1_TSTCLK
L2_TSTCLK
LSSD_MODE
MCP
Y13
W13
U13
W12
Y18
W17
Y17
U16
W14
W15
U14
Y8
A7
M19
L19
M2
L1
D8
A5
K20
J19
N2
N4
N1
P1
P4
P2
R2
R1
U2
T1
B6
PLL_CFG0
PLL_CFG1
PLL_CFG2
PLL_CFG3
PLL_CFG4
PLL_RNG0
PLL_RNG1
QACK
D7
K19
G20
H20
H17
H19
F19
D5
B5
B4
A4
A3
B3
G17
F20
E5
QREQ
U8
RSRV
Y4
SMI
W10
Y7
SRESET
SYSCLK
W16
4. Dimensions and Signal Assignments
Page 28 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003