DD 2.X
PowerPC 750FX RISC Microprocessor
Preliminary
3.3 Spread Spectrum Clock Generator (SSCG)
When designing with the SSCG, there are a number of design issues that must be taken into account.
SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750FX to operate in
this environment, it must be able to accurately track the SSCG clock jitter.
The accuracy to which the 750FX PLL can track the SSCG clock is referred to as tracking skew. When
performing system timing analysis, the tracking skew must be added or subtracted to the I/O timing specifica-
tions because the tracking skew appears as a static phase error between the internal PLL and the SSCG
clock.
To minimize the impact on I/O timings the following SSCG configuration is recommended:
The following SSCG configuration is recommended:
• - Down spread mode, less than or equal to 1% of the maximum frequency
• - A modulation frequency of 30kHz
• - Linear sweep modulation or “Hershey Kiss 1” (as in a Lexmark2 profile) modulation profile as shown in
Figure 3-2 on page 14.
In this configuration the tracking skew is less than 100ps.
Figure 3-2. Linear Sweep Modulation Profile
0%
Down spread
frequency
change
-1%
0µs
33.3µs
Time Increases
1. Hershey Kiss is a trademark of Hershey Foods Corporation.
2. See patent 5,631,920.
3. Electrical and Thermal Characteristics
Page 14 of 63
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
IBM [ IBM ]
