Data Sheet
PowerPC® 750CXr RISC Microprocessor
Contents
1. General Information .................................................................................................... 9
1.1 Features ........................................................................................................................................... 9
1.2 Special Design Level Considerations/Features ......................................................................... 11
1.3 Ordering Information .................................................................................................................... 11
1.4 Processor Version Register (PVR) .............................................................................................. 12
2. Overview .................................................................................................................... 13
2.1 PowerPC 750CXr Block Diagram ................................................................................................. 13
3. General Parameters .................................................................................................. 14
4. Electrical and Thermal Characteristics ................................................................... 15
4.1 DC Electrical Characteristics ....................................................................................................... 15
4.2 AC Electrical Characteristics ....................................................................................................... 19
4.2.1 Clock AC Specifications ........................................................................................................ 19
4.3 Spread Spectrum Clock Generator (SSCG) ................................................................................ 20
4.4 60x Bus Input AC Specifications ................................................................................................. 21
4.5 60x Bus Output AC Specifications .............................................................................................. 22
4.5.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 25
5. PowerPC 750CXr Dimension and Physical Signal Assignments ......................... 27
6. System Design Information ..................................................................................... 35
6.1 PLL Configuration ......................................................................................................................... 35
6.2 PLL Power Supply Filtering ......................................................................................................... 36
6.3 Decoupling Recommendations ................................................................................................... 36
6.4 Connection Recommendations ................................................................................................... 37
6.5 Output Buffer DC Impedance ....................................................................................................... 37
6.5.1 Input-Output Usage ............................................................................................................... 38
6.6 Thermal Management Information .............................................................................................. 41
6.6.1 Thermal Assist Unit ............................................................................................................... 41
6.6.2 Heat Sink Considerations ...................................................................................................... 41
6.6.3 Internal Package Conduction Resistance .............................................................................. 42
6.7 Operational and Design Considerations ..................................................................................... 42
6.7.1 Level Protection ..................................................................................................................... 42
6.7.2 64- or 32-Bit Data Bus Mode ................................................................................................. 43
6.7.3 60x Bus Operation ................................................................................................................. 43
6.7.4 DBWO/L2_TSTCLK ............................................................................................................... 43
6.7.5 CHKSTP_OUT/CLKOUT ....................................................................................................... 43
Revision Log ................................................................................................................ 45
sw_ds_750cxrTOC.fm
February 28, 2005
Page 3 of 43
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