Data Sheet
Preliminary
PowerPC® 750CXr RISC Microprocessor
Table 5-1. Signal Listing for the 256 PBGA Package (Continued)
Signal Name
Pin Count
Active
Low
I/O
I/O
Notes
TS
1
3
TSIZ0–TSIZ2
TT0–TT4
WT
High
High
Low
Output
I/O
5
1
Output
Input
BVSEL
AVDD
1
High
Pin set LOW = +1.8 V, pin set HIGH = +2.5 V
Supply for PLL
1
OVDD
24
40
53
Supply for Receiver/Drivers
Supply for Core
VDD
Ground
Common Ground
Notes:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. The CKSTP_OUT signal in test mode allows viewing the PowerPC 750CXr internal clocks.
The QACK signal allows selection of 32-bit mode.(See the PowerPC 750CXr User’s Manual for more information.)
3. L2-TSTCLK in normal mode is DBWO, for details, see Section 6.7.4 on Page 42.
Table 5-2. PPC750 Signals Not Supported in the 750CXr
Signal Name
Pin Count
Active
Low
Low
Low
Low
Low
High
High
High
High
Low
Low
I/O
I/O
ABB
1
1
1
1
1
1
1
4
8
1
1
DBB
I/O
DBDIS
RSRV
SMI
Input
Output
Input
Input
Output
I/O
TBEN
VOLTDET
AP0–3
DP0–7
DRTRY
TLBISYNC
I/O
Input
Input
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
PowerPC 750CXr Dimension and Physical Signal Assignments
Page 31 of 43
IBM [ IBM ]
