Data Sheet
PowerPC® 750CXr RISC Microprocessor
Preliminary
6. System Design Information
This section provides electrical and thermal design recommendations for successful application of the
PowerPC 750CXr.
6.1 PLL Configuration
PLL-CFG (Table 6-1) must be set so that both SYSCLK and the core frequency are within the Clock AC
Timing Specifications shown in Table 4-6 on page 18. In addition, the core frequency must not exceed the
limit specified in the part number, and the system must meet the required specifications.
Table 6-1. PowerPC 750CXr Microprocessor PLL Configuration
PLL_CFG (0:3)
Processor to Bus Frequency Ratio (r)
Bin
Dec
0
0000
0001
0010
0011
0100
0101
2.5x
1
1
7.5x
7x
2
2
3
PLL Bypass
1
4
2x
5
6.5x
1
9x
0110
6
1
10x
0111
1000
1001
1010
1011
1100
1101
1110
1111
7
4.5x
3x
8
9
5.5x
4x
10
11
12
13
14
15
5x
1
8x
6x
3.5x
3
Off
Notes:
1. The 2x,7.5x, 8x 9x, and 10x Processor to Bus Ratios are currently not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode oper-
ation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
3. In Clock - off mode, no clocking occurs inside the PowerPC 750CXr regardless of the SYSCLK input.
6.2 PLL Power Supply Filtering
The AVDD power signal is provided on the PowerPC 750CXr to provide power to the clock generation phase-
locked loop. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be
filtered using a circuit similar to the one shown in Figure 6-1. The circuit should be placed as close as
System Design Information
Page 34 of 43
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
IBM [ IBM ]
