Data Sheet
PowerPC® 750CXr RISC Microprocessor
Preliminary
4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the PowerPC 750CXr. After fabrication, parts are
sorted by maximum processor core frequency as shown in the Section 4.2.1 on Page 18, and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals.
4.2.1 Clock AC Specifications
Table 4-6 provides the clock AC timing specifications as defined in Figure 4-1.
Table 4-6. Clock AC Timing Specifications1,6 See Table 4-2 on page 15, for recommended operating conditions.
Value
Num
Characteristic
Unit
Notes
Min
300
66
7.5
1.0
25
–
Max
533
133
15
Processor frequency
SYSCLK frequency
SYSCLK cycle time
MHz
MHz
ns
1
1
2, 3
4
SYSCLK rise and fall time (slew rate)
SYSCLK duty cycle measured at 0.8V
SYSCLK jitter
4.0
75
V/ns
%
2, 3
3
150
100
ps
4, 3
5
Internal PLL relock time
–
µs
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency and CPU (core)
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 6.1
“PLL Configuration,” on page 34 for valid PLL_CFG[0:3] settings.
2. Rise and fall times for the SYSCLK input are measured from +0.4 to +1.2 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under 150ps. Contact IBM for use with spread-spectrum clocks or clocks with jitter
in excess of 150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled
and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock
time during the power-on reset sequence.
Figure 4-1. SYSCLK Input Timing Diagram
1
2
3
4
4
CVIH
VM
SYSCLK
CVIL
VM - Midpoint Voltage (+0.85V)
Electrical and Thermal Characteristics
Page 18 of 43
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
IBM [ IBM ]
