Data Sheet
PowerPC® 750CXr RISC Microprocessor
Preliminary
4.4 60x Bus Input AC Specifications
Table 4-7 provides the 60x bus input AC timing specifications for the PowerPC 750CXr as defined in
Figure 4-3 and Figure 4-4.
Table 4-7. 60x Bus Input Timing Specifications1,6 See Table 4-2 on page 15 for operating conditions.
1.8V Mode
Min Max
2.5V Mode
Min Max
Num
10a
Characteristic
Unit
Notes
2
Address/Data/Transfer attribute inputs valid to SYSCLK (input
setup)
1.15
—
1.25
—
ns
ns
10b
10c
All other inputs valid to SYSCLK (input setup)
Mode select input setup to HRESET (QACK)
TS to SYSCLK (input setup)
1.15
8
—
—
—
—
—
—
1.25
8
—
—
—
—
—
—
3
4, 5, 7
—
t
sysclk
10d
1.35
1.5
0.65
0
1.4
1.6
0.3
0
ns
10e
DBWO to SYSCLK (input setup)
ns
ns
ns
—
11a
SYSCLK to inputs invalid (input hold)
HRESET to mode select input hold (QACK)
2
11b
4, 7
Notes:
1. Input specifications are measured from the midpoint voltage of the signal in question to the midpoint voltage of the rising edge of the input SYSCLK.
Input and output timings are measured at the pin (see Figure 4-3). The midpoint voltage used for all pins is 0.85V for 1.8V mode and 1.2V for 2.5V
mode.
2. Address/Data Transfer Attribute inputs are composed of all bidirectional and input signals except those listed in Note 3.
3. All other signal inputs are composed of the following: TA, QACK, and ARTRY.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4-4 on page 21).
5. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design and characterization, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the
PLL relock time during the power-on reset sequence.
Figure 4-3 provides the input timing diagram for the PowerPC 750CXr.
Figure 4-3. Input Timing Diagram
VM
SYSCLK
10a
10b
10d
10e
11a
ALL INPUTS
VM
VM
VM = Midpoint Voltage (+0.85V for 1.8V mode or 1.2V for 2.5V mode)
Electrical and Thermal Characteristics
Page 20 of 43
750cxr_DD4.0_Dev_gen_4_mkt.fm
February 28, 2005
IBM [ IBM ]
