Preliminary Copy
PowerPC 750TM SCM RISC Microprocessor
Decoupling Recommendations
Due to the 750’s dynamic power management feature, large address and data buses, and high operating fre-
quencies, the 750 can generate transient power surges and high frequency noise in its power supply, espe-
cially while driving large capacitive loads. This noise must be prevented from reaching other components in
the 750 system, and the 750 itself requires a clean, tightly regulated source of power. Therefore, it is strongly
recommended that the system designer place at least one decoupling capacitor with a low ESR (effective
series resistance) rating as close as possible to each VDD and OVDD pin (and L2OVDD for the 360 CBGA) of
the 750.
These capacitors should range in value from 220pF to 10µF to provide both high and low frequency filtering.
Suggested values for the VDD pins: 220pF (ceramic), 0.01µF (ceramic), and 0.1µf (ceramic). Suggested val-
ues for the OVDD pins: 0.01µF (ceramic), 0.1µf (ceramic), and 10µF (tantalum). Only SMT (surface-mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feed-
ing the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capaci-
tors should have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100µF (AVX TPS tantalum) or 330µF (AVX TPS tantalum).
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, and GND, pins of the 750.
External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all
SRAMs and at the L2SYNC_IN input of the 750. The L2CLKOUTA network could be used only, or the
L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs.
Output Buffer DC Impedance
The 750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z ,
0
an external resistor is connected to the chip pad, either to OVDD or GND. Then, the value of such resistor is
varied until the pad voltage is OV /2; see Figure 23.
DD
The output impedance is actually the average of two components, the resistances of the pull-up and pull-
down devices. When Data is held low, SW1 is closed (SW2 is open), and R is trimmed until Pad = OVDD/2.
N
R then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is
N
open), and R is trimmed until Pad = OVDD/2. R then becomes the resistance of the pull-up devices. With a
P
P
properly designed driver R and R are close to each other in value. Then Z = (R + R )/2.
P
N
0
P
N
7/15/99
v 3.2
Datasheet
Page 31
IBM [ IBM ]
