PowerPC 750TM SCM RISC Microprocessor
Preliminary Copy
Table 16 provides sample core-to-L2 frequencies.
1
Table 16. Sample Core-to-L2 Frequencies
Core Frequency
÷1
÷1.5
÷2
÷2.5
÷3
(MHz)
200
225
233
250
266
275
300
—
—
—
—
—
—
—
133.3
—
100
112.5
116.5
125
133
—
80
90
—
—
—
93.2
100
106.4
110
120
—
—
83.3
88.6
91.7
100
—
—
—
—
Note:
1. Although the 750 is designed for L2 bus ratios of 1:1, 1.5:1, 2:1, 2.5:1, and 3:1, this specification supports the L2 fre-
quency range specified in Section, “L2 Clock AC Specifications” on page 15. For higher L2 frequencies not supported in
this document, please contact your IBM marketing representative.
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the 750 to provide power to the clock generation
phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the
power supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in
Figure 22. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much
noise as possible. An identical but separate circuit should be placed as close as possible to the L2AVDD pin.
Figure 22. PLL Power Supply Filter Circuit
10 Ohm
VDD
AVDD (or L2AV
)
DD
10 mF
0.1 mF
GND
Page 30
v 3.2
Datasheet
7/15/99
IBM [ IBM ]
