PowerPC 440GP Embedded Processor Data Sheet
Initialization
The PPC440GP provides the option for setting initial parameters based on default values or by reading them
from a slave PROM attached to the IIC0 bus (see “EEPROM” below). Some of the default values can be
altered by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain
default initial conditions prior to PPC440GP start-up. The actual capture instant is the nearest reference clock
edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-
down (logical 0) resistors to select the desired default conditions. They are used for strap functions only
during reset. Following reset they are used for normal functions.
The following table lists the strapping pins along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
V24
(UART0_DCD)
Bootstrap controller
Disabled
Enabled
0
1
V02
(UART0_DSR)
IIC0 slave address that will respond with boot data
0x54
0x50
0
1
EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM
device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the
PPC440GP sequentially reads 16 bytes from the ROM device on the IIC0 port and uses the first 8 bytes to set
the SYS0 and SYS1 registers accordingly. Otherwise, the default values set in the STRP0 and STRP1
registers are used for initialization.
The initialization settings and their default values are covered in detail in the PowerPC 440GP Embedded
Processor User’s Manual.
Page 70 of 72
5/13/04
IBM [ IBM ]
