PowerPC 440GP Embedded Processor Data Sheet
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM
generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP
using a DQS signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by
the system designs using this chip, the three-stage data path shown below is used to eliminate metastability
and allow data sampling to be adjusted for minimum latency. This adjustment requires programming the
Read Clock delay and the selection of Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Mux
RDSP
FF
Package pins
Q
D
PLB bus
ECC
Stage 3
Stage 1
Stage 2
Q
D
Q
D
D
Q
C
FF,
XL
FF
FF
Data
C
C
C
Read Select
(SDRAM0_TR1)
1/4
Cycle
Delay
Programmed
Read Clock
Delay
DQS
PLB Clock
FF Timing:
T
T
= Input setup time = 0.2ns
= Input hold time = 0.1ns
FF: Flip-Flop
XL: Transparent Latch
IS
IH
0.6ns maximum
T = Propagation delay (D to Q or C to Q) =
P
I/O Timing—DDR SDRAM T
and T
DIN
SIN
Notes:
1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. Clock speed for the values in the table is 133MHz.
4. The time values for TSIN include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
T
SIN (ns)
TSIN (ns)
maximum
TDIN (ns)
minimum
TDIN (ns)
maximum
Signal Name
Signal Name
MemData00:07
minimum
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
1.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
MemData08:151
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually
a slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and
signal routing. It is recommended that the signal length for all of the eight DQS signals be matched.
Page 66 of 72
5/13/04
IBM [ IBM ]
