PowerPC 440GP Embedded Processor Data Sheet
System Memory Address Map
Function
Sub Function
Start Address
0 0000 0000
0 8000 0000
0 8000 2000
1 0000 0000
1 4000 0000
1 4000 0200
1 4000 0208
1 4000 0300
1 4000 0308
1 4000 0400
1 4000 0420
1 4000 0500
1 4000 0520
1 4000 0600
1 4000 0640
1 4000 0700
1 4000 0780
1 4000 0790
1 4000 0790
1 4000 0800
1 4000 0900
1 4000 0A00
1 4000 0B00
1 F000 0000
End Address
0 7FFF FFFF
0 8000 1FFF
0 FFFF FFFF
1 3FFF FFFF
1 4000 01FF
1 4000 0207
1 4000 02FF
1 4000 0307
1 4000 03FF
1 4000 041F
1 4000 04FF
1 4000 051F
1 4000 05FF
1 4000 063F
1 4000 06FF
1 4000 077F
1 4000 078F
1 4000 079F
1 4000 07FF
1 4000 08FF
1 4000 09FF
1 4000 0AFF
1 EFFF FFFF
1 FFDF FFFF
Size
2GB
8KB
DDR SDRAM
SRAM
Local Memory1
Reserve
EBC
1GB
8B
Reserved
UART0
Reserved
UART1
8B
Reserved
IIC0
32B
32B
64B
Reserved
IIC1
Reserved
OPB Arbiter
Reserved
Internal Peripherals
GPIO Controller
Ethernet PHY ZMII
Ethernet PHY GMII
Reserved
128B
16B
16B
Ethernet 0 Controller
Ethernet 1 Controller
General Purpose Timer
Reserved
256B
256B
256B
Expansion ROM2
Boot ROM2, 3
254MB
2MB
1 FFE0 0000
2 0000 0000
2 0800 0000
2 0C00 0000
2 0EC0 0000
2 0EC0 0008
2 0EC8 0000
2 0EC8 0100
2 0ED0 0000
2 0EE0 0000
1 FFFF FFFF
2 07FF FFFF
2 0BFF FFFF
2 0EBF FFFF
2 0EC0 0007
2 0EC7 FFFF
2 0EC8 00FF
2 0EC8 00FF
2 0EDF FFFF
F FFFF FFFF
Reserved
PCI-X I/O
64MB
8B
Reserved
PCI-X External Configuration Registers
Reserved
PCI-X
PCI-X Bridge Core Configuration Registers
Reserved
256B
PCI-X Special Cycle
PCI-X Memory
1MB
55.76 GB
Notes:
1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.
2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While
locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 2 FFFE 0000 (128 KB).
Page 7 of 72
5/13/04
IBM [ IBM ]
