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IBM25PPC440GP-3FC400CZ 参数 Datasheet PDF下载

IBM25PPC440GP-3FC400CZ图片预览
型号: IBM25PPC440GP-3FC400CZ
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552]
分类和应用: 时钟外围集成电路
文件页数/大小: 72 页 / 1562 K
品牌: IBM [ IBM ]
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PowerPC 440GP Embedded Processor Data Sheet  
• Supports initiation of transfer to the following address spaces:  
– Single beat I/O reads and writes  
– Single beat and burst memory reads and writes  
– Single beat configuration reads and writes (type 0 and type 1)  
– Single beat special cycles  
DDR SDRAM Memory Controller  
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs and  
other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global  
memory timings, address and bank sizes, and memory addressing modes are programmable.  
Features include:  
• Registered and non-registered industry standard DIMMs and other discrete devices  
• 32- or 64-bit memory interface with optional 8-bit ECC (SEC/DED)  
• Sustainable 2.1GB/s peak bandwidth at 133MHz  
• SSTL_2 logic  
• 1 to 4 chip selects  
• CAS latencies of 2, 2.5 and 3 supported  
• PC200/266 support  
• Page mode accesses (up to eight open pages) with configurable paging policy  
• Programmable address mapping and timing  
• Hardware and software initiated self-refresh  
• Power management (self-refresh, suspend, sleep)  
External Peripheral Bus Controller (EBC)  
Features include:  
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported  
• Up to 66.66MHz operation (266MB/s)  
• Burst and non-burst devices  
• 8-, 16-, 32-bit byte-addressable data bus  
• 32-bit address, 4GB address space  
• Peripheral Device pacing with external “Ready”  
• Latch data on Ready, synchronous or asynchronous  
• Programmable access timing per device  
– 256 Wait States for non-burst  
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses  
– Programmable CSon, CSoff relative to address  
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS  
• Programmable address mapping  
• External master interface  
– Write posting from external master  
– Read prefetching on PLB for external master reads  
– Bursting capable from external master  
– Allows external master access to all non-EBC PLB slaves  
– External master can control EBC slaves for own access and control  
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5/13/04  
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