Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments (Part 3 of 3)
Function
Option
Ball Strapping
ROM Location
U2
HoldAck
PPC405GPr Peripheral Attach
PPC405GPr PCI Attach
0
1
PCI Asynchronous Mode
Enable
Y3
ExtAck
Synchronous PCI Mode
Asynchronous Mode
0
1
External Bus Synchronous
Mode Enable
A22
GPIO3[TS1O]
3
Synchronous Mode
Asynchronous Mode
0
1
3
AF18
GPIO4[TS2O]
PCI Arbiter Enable
Internal Arbiter Disabled
Internal Arbiter Enabled
0
1
New Mode Enable
In Legacy mode the
PPC405GPr functions like the
PPC405GP.
D20
GPIO24
Legacy (PPC405GP) mode
0
If not strapped, the
PPC405GPr defaults to
Legacy mode.
4
1
New (PPC405GPr) mode
Flip Circuit Disable
AB3
(must be strapped low (0)
during initilization).
GPIO9[TrcClk]
Normal operation
0
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr,
visit the technical documents area of the IBM PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in
“Clocking Specifications” on page 42. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr
Embedded Processor User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by
using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
4. The pull-up initialization strapping resistor must be 1kΩ rather than 3kΩ in order to overcome the internal pull-down resistor.
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IBM [ IBM ]
