Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
I/O Specifications—Group 2 (Part 1 of 2)
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the
PPC405GPr IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk timing is specified with a 10pF load at the package pin.
5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10%
and 90% points of the output voltage.
6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
SDRAM Interface
BA1:0
na
na
na
na
na
na
1.4
na
1.4
na
na
na
na
na
na
na
na
0
4.5
4.5
4.4
3.9
4.5
4.3
4.5
4.6
5.1
4.4
4.4
1.6
1.5
1.5
1.4
1.4
1.4
1.5
1.5
1.4
1.5
1.5
15.3
15.3
15.3
23
10.2
10.2
10.2
19.3
10.2
10.2
10.2
10.2
10.2
10.2
10.2
MemClkOut 1, 2, 5
MemClkOut 2, 5
MemClkOut 1, 2, 5
BankSel3:0
CAS
ClkEn0:1
DQM0:3
MemClkOut
MemClkOut
MemClkOut
MemClkOut
2, 5
2, 5
2, 5
2, 5
15.3
15.3
15.3
15.3
15.3
15.3
15.3
DQMCB
ECC0:7
MemAddr12:0
MemData0:31
RAS
na
0
MemClkOut 1, 2, 5
MemClkOut 2, 5
na
na
MemClkOut 1, 2, 5
MemClkOut 1, 2, 5
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
na
3.2
dc
na
0
6.1
na
2.2
na
2
10.3
na
7.1
na
PerClk
PerClk
PerClk
PerClk
PerClk
5
5
5
5
5
dc
0
6.4
7.1
6.5
10.3
15.3
10.3
7.1
10.2
7.1
2.2
3.3
2
0
2.3
PerCS0
PerCS1:7[GPIO10:16]
na
na
6.5
2.1
10.3
7.1
PerClk
5
PerData0:31
PerOE
4.7
na
0.9
na
0
7.2
6.5
7.2
6.6
na
1.9
2.1
2.1
2.1
na
15.3
10.3
15.3
10.3
na
10.2
7.1
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
5
5
5
5
5
5
PerPar0:3
PerR/W
2.3
3.3
5.5
2.3
10.2
7.1
0
PerReady
PerWBE0:3
0
na
0
6.1
2.2
10.3
7.1
49
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