Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is
read to enable default initial conditions prior to PPC405GPr start-up. The actual capture instant is the nearest
SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or
pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to
+3.3V or 10kΩ to +5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions
only during reset. They are used for other signals during normal operation. The following tables list the
strapping pins along with their functions and strapping options. The signal names assigned to the pins for
normal operation follow the pin number.
The PPC405GPr can be used as a replacement for the PPC405GP. When the PPC405GPr is used for this
purpose, it should be strapped to operate in the PPC405GPr Legacy Mode. This option is selected by
strapping ball D20 (GPIO24) low (0). If Legacy Mode is selected, the “PPC405GPr Legacy Mode Strapping
Pin Assignments” table should be used to determine the strapping options. To operate the chip as a
PPC405GPr, strap D20 (GPIO24) high (1) and use “PPC405GPr New Mode Strapping Pin Assignments” on
page 53 to determine the strapping options.
PPC405GPr Legacy Mode Strapping Pin Assignments (Part 1 of 2)
Function
Option
Ball Strapping
AF2
1
AF3
AD16
PLL Tuning
UART0_Tx
UART0_DTR UART0_RTS
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
Choice 1; TUNE[9:0] = 1010111100
Choice 2; TUNE[9:0] = 0100111000
Choice 3; TUNE[9:0] = 0100110110
Choice 4; TUNE[9:0] = 0100111100
Choice 5; TUNE[9:0] = 0100111000
Choice 6; TUNE[9:0] = 1000111100
Choice 7; TUNE[9:0] = 1000111110
Choice 8; TUNE[9:0] = 1011111110
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
D16
DMAAck0
B15
DMAAck1
PLL Forward Divider
Bypass mode
Divide by 3
Divide by 4
Divide by 6
0
0
1
1
0
1
0
1
2
B14
DMAAck2
C12
DMAAck3
PLL Feedback Divider
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
P25
EMCTxD3
L24
EMCTxD2
PLB Divider from CPU
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
51
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